on 06/02/2012 09:04 Alexander Motin said the following:
> I've analyzed scheduler behavior and think found the problem with HTT. SCHED_ULE
> knows about HTT and when doing load balancing once a second, it does right
> things. Unluckily, if some other thread gets in the way, process can be easily
> pushed out to another CPU, where it will stay for another second because of CPU
> affinity, possibly sharing physical core with something else without need.
> I've made a patch, reworking SCHED_ULE affinity code, to fix that:
> http://people.freebsd.org/~mav/sched.htt.patch >
> This patch does three things:
> - Disables strict affinity optimization when HTT detected to let more
> sophisticated code to take into account load of other logical core(s).
> - Adds affinity support to the sched_lowest() function to prefer specified
> (last used) CPU (and CPU groups it belongs to) in case of equal load. Previous
> code always selected first valid CPU of evens. It caused threads migration to
> lower CPUs without need.
> - If current CPU group has no CPU where the process with its priority can run
> now, sequentially check parent CPU groups before doing global search. That
> should improve affinity for the next cache levels.
I know that you are working on improving this patch and we have already
discussed some ideas via out-of-band channels.
Here's some additional ideas. They are in part inspired by inspecting
Let's assume that one of the goals of a scheduler is to maximize system
performance / computational throughput[*]. I think that modern SMP-aware
schedulers try to employ the following two SMP-specific techniques to achieve that:
- take advantage of thread-to-cache affinity to minimize "cold cache" time
- distribute the threads over logical CPUs to optimize system resource usage by
minimizing[**] sharing of / contention over the resources, which could be
caches, instruction pipelines (for HTT threads), FPUs (for AMD Bulldozer
It seems that on modern CPUs the caches are either inclusive or some smart "as
if inclusive" caches. As a result, if two cores have a shared cache at any
level, then it should be relatively cheap to move a thread from one core to the
other. E.g. if logical CPUs P0 and P1 have private L1 and L2 caches and a
shared L3 cache, then on modern processors it should be much cheaper to move a
thread from P0 to P1 than to some processor P2 that doesn't share the L3 cache.
If this assumption is really true, then we can track only an affinity of a
thread with relation to a top level shared cache. E.g. if migration within an
L3 cache is cheap, then we don't have any reason to constrain a migration scope
to an L2 cache, let alone L1.
I think that the current balancing code is pretty good, but can be augmented
with the following:
A. The SMP topology in longer term should include other important shared
resources, not only caches. We already have this in some form via
CG_FLAG_THREAD, which implies instruction pipeline sharing.
B. Given the affinity assumptions, sched_pickcpu can pick the best CPU only
among CPUs sharing a top level cache if a thread still has an affinity to it or
among all CPUs otherwise. This should reduce temporary imbalances.
[*] Goals of a scheduler could be controlled via policies. E.g. there could be
a policy to reduce power usage.
[**] Given a possibility of different policies a scheduler may want to
concentrate threads. E.g. if a system has two packages with two cores each and
there are two CPU-hungry threads, then the system may place them both on the
same package to reduce power usage.
Another interesting case is threads that share a VM space or otherwise share
some non-trivial amount of memory. As you have suggested, it might make sense
to concentrate those threads so that they share a cache.
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